1. Field of the Invention
The present invention relates to a digital phase-locked loop circuit.
2. Description of the Related Art
An all-digital phase-locked loop (hereinafter referred to as ADPLL) circuit is disclosed in JP-A-2002-76886. FIG. 11 illustrates the configuration of an ADPLL circuit in which the circuit disclosed in JP-A-2002-76886 is simplified to be operated similarly thereto. An ADPLL circuit 10 illustrated in FIG. 11 includes a time-to-digital converter (TDC circuit) 1, a digitally-controlled-oscillator (DCO) circuit 7, a flip-flop (FF) circuit 2, accumulators 3 and 4, a phase difference calculating circuit 6, a normalization processing circuit 5, and a digital filter 9.
The following briefly describes the operation of the ADPLL circuit 10. The reference clock FREF is inputted to the clock input terminal of the TDC circuit 1 and the data input terminal of the FF circuit 2. The output clock CKV output from the DCO circuit 7 is inputted to the clock input terminal of the FF circuit 2. Therefore, the reference clock FREF adjusted in timing according to the output clock CKV is inputted to the clock terminal of a latch circuit and an accumulator 3 as a clock CKR. The accumulator 3 accumulates multiple set values each time the clock CKR is inputted. The accumulator 4 accumulates the output clock CKV one by one each time it is inputted.
The TDC circuit 1 outputs a phase difference as digital data between the reference clock FREF and the output clock CKV in the timing of the reference clock FREF. The digital data indicates the phase difference between the reference clock FREF and the output clock CKV by the number of delay elements of the TDC circuit 1. FIG. 12 illustrates the configuration of the TDC circuit 1. The TDC circuit 1 includes L pieces of the delay elements, L pieces of the FF circuits, and an edge detector. FIG. 13 is a timing chart indicating the operation of the TDC circuit 1. The number of the delay elements L is taken as 10. As illustrated in FIG. 13, the clock signals D(0) to D(L−1) in which the output clock CKV is gradually delayed by the L pieces of the delay elements are sampled all at once by the rising edge of the reference clock FREF at time t1. In the example illustrated in FIG. 13, a value of “0011110000” is obtained as a sampling data Q[0:9] (L=10). Places where the value is changed from “0” to “1” and from “1” to “0” of the sampling data Q[0:9] are detected to enable representing an interval between the rising edge and the falling edge of the delayed output clock CKV by the number of stages of the delay elements. In other words, the place Q(2) where the value is changed from “0” to “1” represents information of the falling edge and the place Q(6) where the value is changed from “1” to “0” represents information of the rising edge. The edge detector outputs these pieces of information as digital data TDC_FALL and TDC_RISE.
The phase difference calculating circuit 6 calculates one period of the output clock CKV according to the digital data TDC_FALL and TDC_RISE. The above calculation method is described below with reference to the schematic diagrams of FIGS. 14 and 15. FIG. 14 shows the case where the output clock CKV advances in phase by Φ with respect to the reference clock FREF. FIG. 15 shows the case where the output clock CKV is delayed in phase by Φ with respect to the reference clock FREF. As illustrated in FIGS. 14 and 15, a difference between a term ΔTr of the rising edge of the output clock CKV with respect to the rising edge of the reference clock FREF and a term ΔTf of the falling edge of the output clock CKV with respect to the rising edge of the reference clock FREF is equal to half a period of the output clock CKV. The ADPLL circuit 10 detects the terms ΔTr and ΔTf as the number of stages of the delay elements.
In other words, (TDC_RISE−TDC_FALL) is detected as a half period of the output clock CKV. One period is calculated as a value in which (TDC_RISE−TDC_FALL) is doubled. The number of delay stages being a phase difference between the reference clock FREF and the output clock CKV is normalized by using the calculation result. The normalized phase difference can be represented by the following equation:
Phase difference=TDC_RISE/(2×(|TDC_RISE−TDC_FALL|)). This equation allows converting the phase difference represented by the number of the delay elements in the TDC circuit 1 to a ratio with respect to one period of the output clock CKV.
The phase difference calculating circuit 6 digitally processes accumulated values of the accumulators 3 and 4 and the value of phase difference within one period of the output clock CKV from the phase difference calculating circuit 6. Specifically, (the accumulated value of the reference clock FREF)−(the accumulated value of the output clock CKV)−(phase difference value) is digitally processed to be taken as phase error data. The phase error data is smoothed by the digital filter 9. The oscillation frequency of the output clock CKV output by the DCO circuit 7 in response to the output of the digital filter 9 is adjusted. The feedback loop with the aforementioned circuit configuration adjusts the phase error between the reference clock FREF and the output clock CKV to zero, allowing providing the output clock CKV stable in frequency.